Field of the Invention
Embodiments of the present invention relate generally to integrated circuit testing and, more specifically, to virtual access of input/output (I/O) for test via an on-chip star network.
Description of the Related Art
At various stages of the manufacturing process for integrated circuits (ICs), various tests are performed to ensure that the integrated circuits meet or exceed certain specifications. In particular, manufacturers employ automated test equipment (ATE) systems to perform input leakage tests and DC parametric tests on each input/output (I/O) pad of each integrated circuit. These DC parametric tests include input voltage level threshold tests (also referred to herein as VIH/VIL tests) and output drive strength tests (also referred to herein as VOH/VOL tests).
Typically, the integrated circuit that is undergoing test is mounted to a particular load board, where the load board facilitates the connection of each I/O pad of the integrated circuit to a different ATE test channel of the of the ATE system. The load board is customized to the form factor of the integrated circuit undergoing test. As one example, a semiconductor wafer that includes multiple integrated circuits undergoing test could be mounted to one type of load board, whereas one or more packaged integrated circuits undergoing test could be mounted to a different type of load board. In general, the ATE system includes one ATE test channel for each I/O pad of the integrated circuit. During testing, the ATE system makes contact with each I/O pad of the integrated circuit through the load board via a different ATE test channel. As the complexity of integrated circuits has increased over time, the number of I/O pads on a typical integrated circuit has likewise increased. Consequently, complex integrated circuits having hundreds or even thousands of I/O pads are not uncommon. As a further consequence, the ATE system likewise needs hundreds or thousands of channels in order to make contact with and perform leakage and DC parametric testing on each I/O pad of the integrated circuit via the load board.
One drawback of conventional integrated circuit testing is that the cost of ATE systems increases significantly as the number of ATE test channels increases. Thus, performing IO leakage testing on more complex integrated circuits with high I/O pad counts typically involves very expensive ATE systems. Because of the high expense, relatively few of these more complex ATE systems are in circulation. As a result, companies that develop and manufacturer complex integrated circuits either do not have or cannot afford to purchase or rent such ATE systems in sufficient quantities to support large volume test capacity.
One possible solution to this problem is to design customized load boards with mechanical relays that permit one ATE test channel to perform tests on multiple I/O pads. For example, if the load board included one relay for every two or more pins, the ATE system could latch the relays in one position to test one portion of the pins on the integrated circuit. The ATE system could then latch the relays in another position to test a second portion of the pins. The ATE system could then latch the relays in yet another position to test a third portion of the pins, and so on, until all pins are tested. In this manner, a developer and manufacturer of complex integrated circuits is able to use ATE systems that have a fewer number of ATE channels than otherwise needed. Such ATE systems are more plentiful and less expensive to purchase or rent.
One drawback to these possible solutions is that mechanical relays are slow in response time, leading to longer test times. Another drawback to these possible solutions is that relays are expensive and have limited useful lives. That is, a load board that includes mechanical relays needs to be replaced after a specified number of test cycles, because the mechanical relays have reached the limits of reliable use. On the other hand, load boards that do not include mechanical relays typically have relatively long useful lives, and, therefore, are replaced at much longer intervals. As a result, the use of load boards with mechanical relays leads to higher test costs relative to using load boards without mechanical relays.
As the foregoing illustrates, what is needed in the art is a more effective approach for testing integrated circuits.